MLD215 - SampleFlex FIR Filter
FIR Filters are widely used in DSP systems, however due to the high fanout nature they can be challenging to operate at high frequencies. As is true with all the SampleFlex line of IP cores, this problem is easily solved by handling multiple samples at every clock cycle.
Unlock sample rates >> fMax by consuming multiple samples per clock.
Inputs and outputs are highly adjustable with paramaters to fit your designs to ease integration. Change many parameters at compile time to chose your own trade offs.
Paramaterized N sample per clock processing
Paramaterized data I/O size
Paramaterized flop stages
Parameterized coefficientbit width
Dynamic tap coefficients
Dynamic bit growth
Dynamic gain adjustment
Increase parallelization to reduce fdev
Decide how many stages are required to fit your system’s need
Easy integration with flexible I/O