MLD221 - SampleFlex Digital Down Converter


MLD221 core combines the MLD201 Mixer, MLD211 CIC Decimator, and MLD215 FIR filter to achieve a complete high performance ultra wideband scalable digital down conversion (DDC) chain.

Unlock sample rates >> fMax by consuming multiple samples per clock. Reduce samples consumed per clock throughout the core to decrease area when using higher decimation factors.

Inputs and outputs are highly adjustable with paramaters to fit your designs to ease integration. Change many parameters at compile time to chose your own trade offs.

As always, all our IP cores comes with the source Verilog to allow for deeper configuration and customization.

Unlock Oversampling Resolution Gain by outputting larger data widths then the input.



  • Paramaterized N sample per clock processing throughout the core for optimal performance and area

  • Paramaterized Noise Characteristics

  • Paramaterized data I/O size

  • Paramaterized flop stages

  • Increase parallelization to reduce fdev

  • Decide how many stages are required to fit your system’s need

  • Easy integration with flexible I/O

  • MATLAB Application (no license required) to generate custom DDC blocks

  • Python Based DSP Testing Platform

Configure Matlab App
based on project


Generate the
Verilog Source
code and review

Analyze the
frequency response


Send your own data
through the generated
Verilog using python
based test platform

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