MLD222 - SampleFlex Digital Up Converter

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MLD222 core combines the MLD201 Mixer, MLD212 CIC Interpolator, and MLD215 FIR filter to achieve a high performance, ultra wideband scalable digital up converter (DUC) chain.

Unlock sample rates >> fMax by consuming multiple samples per clock. Increase samples consumed per clock throughout the core to decrease area when using higher interpolations factors (start with single samples per cycle and gradually increase palatalization throughout core to reach very high sample rates while optimizing area.).

Inputs and outputs are highly adjustable with paramaters to fit your designs to ease integration. Change many parameters at compile time to chose your own trade offs.

As always, all our IP cores comes with the source Verilog to allow for deeper configuration and customization.

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Features

  • Paramaterized N sample per clock processing throughout the core.

  • Paramaterized Noise Floor Characteristics

  • Paramaterized data I/O size

  • Paramaterized flop stages

  • Increase parallelization to reduce fdev

  • Decide how many stages are required to fit your system’s need

  • Easy integration with flexible I/O

  • MATLAB Application (no license required) to generate custom DUC blocks

  • Python based testing platform


Configure Matlab App
based on project
requirements

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Generate the
Verilog Source
code and review
characteristics

Analyze the
frequency response

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Send your own data
through the generated
Verilog using python
based test platform

 
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